The present invention relates to a method of driving a nonvolatile semiconductor storage device such as an electrically alterable flash memory.
Conventionally, a variety of flash memories having different memory cell structures and driven in different ways have been developed as nonvolatile semiconductor storage devices, by virtue of their capability of higher integration. These flash memories are classified into two groups depending on the following two program/erase driving methods:
(1) employing CHE (channel hot electron) injection for programming and employing FN (Fowler-Nordheim) tunneling for erasing; and PA1 (2) employing FN (Fowler-Nordheim) tunneling for both programming and erasing. PA1 (a) AND Type Flash Memory; PA1 (b) DI (Divided bit line) NOR Type Flash Memory; PA1 (c) ACEE (Advanced Contactless EEPROM) Type Flash Memory; PA1 (d) FN-FN Type Flash Memory With Select Gate; and PA1 (e) NAND Type Flash Memory PA1 in programming a memory cell, the corresponding second MOS transistor is turned off to disconnect the local source line connected with the memory cell from the common source line, the first MOS transistor is turned on to connect the local bit line connected with the memory cell with the corresponding main bit line, and a specified voltage is applied to the corresponding main bit line and a predetermined voltage is applied to the word line connected with the memory cell such that the specified voltage on the main bit line is applied to the drain of the memory cell and then to the channel region and source thereof. PA1 (a) in an programming operation, PA1 (b) in an erasing operation,
The method (1) is the most common method for flash memories, and particularly for ETOX (EEPROM with tunnel oxide) type flash memories. The memory cell structure (one-transistor type) of the ETOX type flash memory is shown in FIG. 16. This flash memory includes a source 52, a drain 53, a floating gate 55, a control gate 57, and a channel region between the source 52 and the drain 53. Also, an interlayer insulating film 56 is provided between the control gate 57 and the floating gate 55, and a tunnel oxide 54 is provided between the floating gate 55 and the channel region. An n.sup.- region 58 is formed between the source 52 and the semiconductor substrate 1, while a p.sup.+ region 59 is formed between the drain 53 and the semiconductor substrate 1. The ETOX type flash memory is basically of the DDD (double doped drain) structure so that a high voltage is able to be applied. On the drain 53 side, there occur hot electrons at a high efficiency in the vicinity of the drain 53 due to the p.sup.+ region 59. That is, the structure of the ETOX type flash memory is characterized by being asymmetric.
Table 1 shows applied voltage conditions of the memory cell of the ETOX type flash memory.
TABLE 1 ______________________________________ Gate Drain Source Substrate ______________________________________ Program 12 6 0 0 Erase -10 F 5 0 Read 5 1 0 0 ______________________________________ Unit: V F: Floating
For programming of the memory cell in the ETOX type flash memory, channel hot electrons are generated in the vicinity of the drain 53 by using the applied voltage conditions shown in table 1, so that electrons are injected into the floating gate 55. For erasing, a high electric field is generated at a portion where the source 52 and the floating gate 55 overlap each other, by which the electrons are extracted from the floating gate 55 by the FN tunneling phenomenon.
FIG. 17 shows endurance characteristics of the ETOX type flash memory, indicating that the endurance characteristics deteriorate with repeated erase/program operations. That is, when the number of erase/program operations exceeds 10.sup.3, a threshold voltage Vth in the high threshold state (programming state) gradually decreases, while the threshold voltage Vth in the low threshold state (erase state) gradually increases. This is because electrons or holes are trapped in the tunnel oxide 54 during repeated erase/program operations.
FIG. 18 shows a memory cell array of NOR type structure in the ETOX type flash memory. The distribution of the threshold voltage Vth in the ETOX type flash memory, which is shown in FIG. 19, indicates that the erased state (with data "1") is a low threshold voltage Vth state and that the programmed state is a high threshold voltage Vth state.
First, in the case of a program sequence, the timing charts of which are shown in FIGS. 20A, 20B and 20C, a positive high voltage Vpp (e.g., +12 V) is applied to a word line WL with which a memory cell to be programmed is connected (FIG. 20A). In this case, for writing data "0", a positive high voltage Vpd (e.g., +6 V) is applied to a relevant bit line BL (FIG. 20B), and a voltage Vss (e.g., 0 V) is applied to a common source line CSL (FIG. 20C), so that very high energy electrons, i.e., channel hot electrons (CHE) are generated. With these high energy electrons injected to the floating gate, the threshold voltage Vth grows high. In this programming sequence, because a large current (0.5 mA/cell) flows through the channel region, the number of memory cells that can be programmed at the same time is limited to around 16.
In this connection, in a flash memory described later wherein both erase and program operations are performed by the Fowler-Nordheim (FN) tunneling, the current used for programming is 10 nA /cell or smaller so that memory cells of 1 K bits or more can be programmed at one time. In this case, in loading data "0", because the voltage Vss (e.g., 0 V) is applied to the bit line, there occur no channel hot electrons so that the threshold voltage Vth is held at the low state.
In the case of an erase sequence, on the other hand, the timing charts of which are shown in FIGS. 21A, 21B and 21C, a positive high voltage Vps (e.g., 5 V) is applied to the common source line CSL (FIG. 21C) and then a negative voltage Vnn (e.g., -10 V) is applied to the word line WL (FIG. 21A). When this is done, the voltage Vss (e.g., 0 V) is applied to the bit line BL (FIG. 21B). As a result, all the memory cells M00-Mnm have a high electric field generated at a portion where the source and the floating gate overlap each other, so that electrons are extracted from the floating gate to the source, with the result that the threshold voltage is lowered.
The flash memories employing the above method (2) are typified by the following five, which differ in structure of the memory cell array:
These (a) to (e) are explained below one by one.
(a) AND Type Flash Memory
An AND type flash memory has been reported in Technical Report of IEICE (THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS), ICD 93-128, pp. 37-43 (1993). A similar technique has also been reported in Japanese Patent Laid-Open Publication HEI 6-77437. This AND type flash memory has a basic structure of memory cells identical to that of the memory cell shown in FIG. 16, and the following description is made referring to this figure.
Table 2 shows applied voltage conditions of the AND type memory cell.
TABLE 2 ______________________________________ Gate Drain Source Substrate ______________________________________ Program -9 4 0 0 Erase 12 F F 0 Read 3 1 0 0 ______________________________________ Unit: V, F: Floating
For programming the AND type memory cell, a high electric field is generated at a portion where the drain 53 and the floating gate 55 overlap each other, as obvious from the applied voltage conditions of Table 2, so that electrons are extracted from the floating gate 55 to the drain 53. For erasing, on the other hand, electrons are induced in the channel region between the source 52 and the drain 53, and a high electric field is generated between the channel region and the floating gate 55. As a result, electrons are injected to the floating gate 55 via the tunnel oxide 54.
(b) DINOR Type Flash Memory
The DINOR type flash memory has been reported in the IEEE Journal of Solid-State Circuits, Vol. 9., No. 4, pp. 454-459 (1994). This DINOR type flash memory also has a basic structure of memory cells identical to that shown in FIG. 16, and so the following description is made with reference to FIG. 16.
Table 3 shows applied voltage conditions of the DINOR type flash memory.
TABLE 3 ______________________________________ Gate Drain Source Substrate ______________________________________ Program -8 5 0 0 Erase 8 F -8 -8 Read 3 1 0 0 ______________________________________ Unit: V, F: Floating
For programming the DINOR type flash memory, as obvious from the applied voltage conditions of Table 3, a high electric field is generated at a portion where the drain 53 and the floating gate 55 overlap each other, so that electrons are extracted to the drain 53. For erasing, on the other hand, electrons are injected from the semiconductor substrate 51 and the source 52 to the floating gate 55 via the tunnel oxide 54.
FIG. 22 shows endurance characteristics of (a) the AND type flash memory and (b) the DINOR type flash memory. In the AND type flash memory and the DINOR type flash memory, both the erase characteristics and the programming characteristics deteriorate due to repeated erase/program operations as in the case of the ETOX type flash memory.
There is a report on a method of preventing such deterioration of endurance characteristics (IEICE TRANS. ELECTRON, VOL. E79-C, pp. 832-835, 1996). This report shows that in ejecting, or extracting the electrons from the floating gate 55 to reduce the threshold voltage of the memory cells, holes generated in the semiconductor substrate 51 are trapped in the tunnel oxide 54. These trapped holes, as is well known, largely affect the endurance characteristics of memory cells.
FIG. 23 shows endurance characteristics which have been improved by applying a negative electric field for ejection of electrons from the floating gate and then applying a positive electric field, wherein the negative electric field refers to an electric field generated when the voltage on the control gate 57 side in FIG. 16 is lower, and the positive electric field refers to an electric field generated when the voltage on the control gate 57 side is higher. It is considered that the holes trapped in the tunnel oxide 54 with the negative electric field applied may be electrically neutralized by the positive electric field applied, resulting in the improvement in the endurance characteristics. In the flash memories (c)-(e) described below, the endurance characteristics are improved by performing the injection/extraction of electrons in the same tunnel region.
(c) ACEE Type Flash Memory
The ACEE type flash memory uses the same region of the tunnel oxide (IEEE JOURNAL OF SOLID-STATE CIRCUITS Vol. 26, pp. 484-491, 1991).
FIG. 24 shows a basic structure of the memory cell of the ACEE type flash memory. This memory cell has a source 72, a drain 73, a tunnel oxide 74, an oxide 75, a gate oxide 76, a floating gate 77, an interlayer insulating 20 film 78, and a control gate 79, which are formed on a semiconductor substrate 71. The tunnel oxide 74 and the gate oxide 76 are insulated by the oxide 75, and electrons are injected into the floating gate 77 via the tunnel oxide 74, while electrons are extracted from the floating gate 77 via the tunnel oxide 74.
Table 4 shows applied voltage conditions of the memory cell of the above ACEE type flash memory in each operational mode.
TABLE 4 ______________________________________ Gate Drain Source Substrate ______________________________________ Program 18 0 0 0 Erase -11 F 5 0 Read 5 1 0 0 ______________________________________ Unit: V, F: floating
For programming the ACEE type flash memory, with the control gate 79 at +18 V, with the drain 73 and the source 72 at 0 V, electrons are injected into the floating gate 77 via the tunnel oxide 74 on the source 72. For erasing, with the source 72 at +5 V and the control gate 79 at -11 V, electrons are extracted via the tunnel oxide 74.
As described above, in the ACEE type flash memory, the injection and extraction of electrons are performed via the same tunnel oxide 74 on the source 72. FIG. 25 shows endurance characteristics of the memory cell of this ACEE type flash memory, where the program/erase characteristics exhibit little change until after the erase/program cycle has been repeated 10.sup.4 times. This obviously indicates that the characteristics have been improved.
(d) FN--FN Flash Memory With Select Gate
The FN--FN flash memory with select gate has been discussed in Japanese Patent Laid-Open Publication HEI 6-120515. FIG. 26 shows a basic structure of a memory cell of the FN--FN flash memory with select gate. This memory cell has a source 82, a drain 83, a tunnel oxide 84, a floating gate 85, an interlayer insulating film 86, a control gate 87, and a select gate 88, which are formed on a semiconductor substrate 81.
Table 5 shows applied voltage conditions of the above FN--FN flash memory with select gate in each operational mode.
TABLE 5 ______________________________________ Gate Drain Source Substrate Select ______________________________________ Program 18 0 F 0 0 Erase -9 F F 9 F Read 5 1 0 0 5 ______________________________________ Unit: V, F: Floating
For programming the FN--FN flash memory with select gate, the channel region is induced under the floating gate 85, a high electric field is generated between the floating gate 85 and the channel region, and electrons are injected into the floating gate 85. For erasing, on the other hand, a high electric field is generated between the floating gate 85 and the semiconductor substrate 81. As a result, electrons are extracted (hole injection).
In the above FN--FN flash memory with select gate, the injection/extraction (hole injection) of electrons is performed via the same region of the tunnel oxide 84 between the channel region and the floating gate 85. Therefore, relatively good endurance characteristics can be obtained as shown in FIG. 26.
(e) NAND Type Flash Memory
The NAND type flash memory is the most common of the FN--FN flash memories. In this memory, a tunnel oxide between the channel region and the floating gate is used for programming/erasing. FIG. 28 shows the arrangement of a memory cell array of the NAND type flash memory, where memory cells Mxy are arrayed in a matrix form. Gates of the memory cells Mxy in an identical row are commonly connected with a word line WL0, . . . , WL15, while the sources and the drains of the memory cells Mxy in an identical column are connected to one another. The drains of the memory cells Mxy in the uppermost row in the figure are connected with bit lines BL0-BL2047 via respective select transistors ST. The sources of the memory cells Mxy in the lowermost row are commonly connected to a common source line SL.
Table 6 shows applied voltage conditions in each operational mode.
TABLE 6 ______________________________________ Gate Drain Source Substrate ______________________________________ Program 21 0 0 0 Erase 0 F F 23 Read 0 5 0 0 ______________________________________ Unit: V, F: Floating
For programming the NAND type flash memory, as obvious from the applied voltage conditions of Table 6, electrons are induced in the channel region, and a high electric field is generated between the floating gate and the channel region, so that electrons are injected into the floating gate. For erasing, on the other hand, a high voltage is applied to the semiconductor substrate, so that a high electric field of a polarity opposite to that in the programming operation is generated. As a result, electrons are extracted from the floating gate. In the NAND type flash memory, relatively good endurance characteristics are obtained, as shown in FIG. 29
FIG. 30 shows a distribution of the threshold voltage of the memory cell in programming/erasing in the NAND type flash memory. For a read operation of the NAND type flash memory, a voltage of 0 V is applied to a word line connected with a memory cell to be read, while a voltage of +5 V is applied to word lines connected with non-selected memory cells.
In addition to the above types of (a) to (e), the flash memory using the FN tunneling for programming/erasing includes another type in which the source and drain are formed in a well layer (see Japanese Patent Laid-Open Publication HEI 8-279566). FIG. 31 shows a basic structure of a memory cell of such a flash memory in which a source and a drain are formed in a well layer. In this memory cell, an n-well layer 92 and a p-well layer 93 are formed on a semiconductor substrate 91, and a source 94 and a drain 95 are formed in the p-well layer 93. On the p-well layer 93, source 94 and drain 95 are formed a tunnel oxide 96, a floating gate 97, an interlayer insulating film 98 and a control gate 99.
Table 7 shows applied voltage conditions for each mode of the flash memory in which the source and the drain are formed in the well layer.
TABLE 7 ______________________________________ Gate Drain Source Well ______________________________________ Program 12 *-3/3 F -3 Erase -9 6 F 6 Read 3 1 0 0 ______________________________________ *for data 0/for data 1 Unit: V, F: Floating
In this flash memory, for programming, as shown in Table 7, the p-well layer 93 is biased to a negative voltage, while the drain 95 has a negative voltage applied thereto. This flash memory can be operated with a memory cell array arrangement similar to that shown in FIG. 3. In programming, a voltage of -3 V or +3 V is applied to the drain in accordance with data of "0" or "1". With -3 V applied to the drain 95, a high electric field is generated across the channel region and the floating gate between the source 94 and the drain 95, so that electrons are injected into the floating gate. With +3 V applied to the drain, the electric field is relaxed so that electrons are not injected to the floating gate.
In the ETOX type, AND type, and DINOR type flash memories that have been described hereinabove, the region of the tunnel oxide through which electrons are passed differs between the programming operation and the erasing operation, thus having a problem of large deterioration of endurance characteristics. Further, in these devices, because high voltages are applied to the drain and the source for the extraction of electrons, a tunneling (Band-to-Band) current flows accordingly, so that hot holes are generated. These hole holes are trapped by the tunnel oxide, causing the endurance characteristics to be deteriorated.
Also, a high voltage must be applied to the drain or the source for enhancement of the efficiency of electron extraction. However, in order for a punch through effect not to occur, such parts must be formed in a large area to ensure the resistance to high voltage. This would result in a problem of increased layout area.
On the other hand, the ACEE type flash memory and the FN--FN flash memory with select gate use the same region of the tunnel oxide for both programming and erasing, so that the endurance characteristics are improved. However, as can be understood from the basic structure of the memory cells shown in FIGS. 24 and 26, the effective area per memory cell is comparatively large (about 1.5 to 3 times that of the ETOX type), which would obstruct the higher degree of integration of flash memories.
Also, in the NAND type flash memory, which is superior in terms of high integration and endurance characteristics, as can be understood from the arrangement of its memory cell array, data is output to a bit line via channel regions of non-selected memory cells up to a memory cell to be read. Accordingly, resistors and capacities connected with the bit line increase, causing the access speed to be considerably reduced. For example, the NOR type flash memory has an access time of around 100 ns, while the NAND type flash memory has that of around 10 .mu.s, which is about 100 times longer. That is, the NAND type flash memory is incapable of offering a high access speed. Further, the investigation of the operating region (a region where electrons pass) of the NAND type flash memory indicates that programming is done by electrons being injected from the source, drain and channel layers. Erasing, on the other hand, is done by electrons being extracted from the floating gate substantially only into the channel region because the source and drain are in the floating state. That is, between the drain/source and the floating gate, only the electron injection is done, and electrons remain trapped at this part (i.e. in the oxide on the source and drain). This could affect the endurance characteristics and reliability if erase/program operations are repeated as many as more than one million times.
Further, in the flash memory in which the source and the drain are formed in the well layer, there are formed several M (=10.sup.6) of memory cells. Since a negative voltage is applied to the p-well layer 93 during programming, a capacity of several thousand pf is added to the p-well layer 93, causing the rise of signals to be much slow, resulting in an access speed for programming being considerably lowered. Furthermore, since a positive voltage and a negative voltage are selectively applied to the bit lines, it is necessary to form on a triple well a data latch circuit or the like for selecting voltages to be applied to the bit lines. This would result in increase in the layout area.